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The SPI bus specifies four logic signals:
- SCLK : Serial Clock (output from master).
- MOSI : Master Output, Slave Input (output from master).
- MISO : Master Input, Slave Output (output from slave).
- SS : Slave Select (active low, output from master).
Alternative naming conventions are also widely used, and SPI port pin names for particular IC products may differ from those depicted in these illustrations:
- SCLK : SCK, CLK.
Master Output –> Slave Input:
- MOSI : SIMO, SDO (for master devices), SDI(for slave devices), DI, DIN, SI, MTST.
Master Input <– Slave Output:
- MISO : SOMI, SDO (for slave devices ), SDI(for master devices), DO, DOUT, SO, MRSR.
- SS : nCS, CS, CSB, CSN, EN, nSS, STE, SYNC.
The MOSI/MISO convention requires that, on devices using the alternate names, SDI on the master be connected to SDO on the slave, and vice versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise. Slave select is used instead of an addressing concept.